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Thank you for visiting my website.

I am an Associate Professor of Electrical and Computer Engineering at Stony Brook University.

My research combines aspects of hardware design, FPGAs, compilers, and CAD, and focuses on applications in machine learning, DSP, and networking.

I have created and maintain the Spiral DFT/FFT IP Core Generator (opens in new tab), an online tool to generate flexible hardware implementations of the discrete Fourier transform suitable for implementation as ASIC or FPGA.

Updates

Posted occasionally. Click any headline to read more.

• New paper on efficient hardware for sparse attention to appear at FPGA 2026
  February 19, 2026
• New paper on adaptive rate control to appear at IoTDI
  May 12, 2024
• New survey paper on efficient methods for natural language processing published in TACL
  July 12, 2023
• New paper on voltage scaled DNN accelerators published at GLSVLSI
  June 05, 2023
• New paper on hardware acceleration of state machine replication published at NSDI
  April 17, 2023

Read more on the updates page.